In a semiconductor process, during wafer level packaging, different carriers need to be customized according to different die sizes. In the whole manufacturing process, the carrier is used after the die is welded and is separated for recycling until the fan-out process is completed. Therefore, regarding the production efficiency, the applicability and quantity of the carrier always become a bottleneck. However, if the quantity of the spare carrier is increased accordingly, the cost is also increased.
In addition, as 3D packaging is increasingly demanded to meet the growing requirements of electronic elements with reduced sizes, to implement fan-out wafer level packaging without changing the existing machine, apparatuses and carrier is an important issue to be solved to save the cost.